High resolution pwm generator or digitally controlled oscillator

ABSTRACT

A high resolution pulse width modulation (PWM) or voltage controlled output (DCO) generator is disclosed. The resolution is increased over that of the circuit clock by delaying the generated signal through a series of delays, all of which are controlled by a delay locked loop. The delays are a small fraction of the clock period, thus providing resolution greater than that of the circuit clock.

This invention relates to oscillators, and in the preferred embodiment,an improved method and apparatus for use in Pulse Width Modulation (PWM)and Digitally Controlled Oscillator (DCO) circuits. The invention hasparticular applicability in areas where it is desired to increase theresolution of a PWM or DCO without increasing the clock speed.

PWM and DCO circuits are used in a variety of applications, including,for example lamp drivers. Such circuits usually utilize a counter havinga clock input to generate on and off time periods in an output signal.Typically, the contents of the register are compared with a counter, andthe counter is reset each time it reaches the value stored in theregister.

The time resolution of the PWM circuit depends upon the clock frequency.A very high clock frequency results in an improved time resolution.However, increased frequencies of the clock lead to higher powerconsumption and electromagnetic interference (EMI). Additionally, theintegrated circuit (IC) fabrication processes to produce ICs that canoperate as such high frequencies are significantly more expensive thantheir lower frequency counterparts.

Accordingly, there is a need in the art for an improved technique forachieving relatively high time resolution with a relatively low clocksignal for use in PWM and DCO circuits.

FIG. 1 depicts a conventional prior art implementation of a PWM or DCOgenerator;

FIG. 2 shows a schematic of a DCO generator using a relatively low clockrate and relatively high time resolution in accordance with theinvention;

FIG. 3 depicts plural waveforms showing the time resolution resultingfrom the arrangement of FIG. 2;

FIG. 4 depicts an exemplary embodiment of the invention for generating aPWM signal with relatively high time resolution; and

FIG. 5 depicts several graphs showing the relatively high timeresolution of the arrangement of FIG. 4.

FIG. 2 shows a DCO generator with improved time resolution. Thearrangement of FIG. 2 includes the programmable delay 101, a selector102, a microprocessor 103 for controlling the system as shown; delayelements 104-107 arranged with a delay locked loop 108, and a variety ofinterconnections between the foregoing elements. As further described,the circuit permits time resolution higher than the rate of clock 110that is input into the arrangement.

In operation, a clock 110 and signal V_(f) are input into a programmabledelay 101 that has been programmed to delay the input signal V_(f) by aspecified number of clock cycles. After the appropriate delay, aninverted delayed version of the signal V_(f) is placed upon output a₀and fed sequentially through delay elements b1-bn. A delay locked loop108 is connected to delay elements 104-107 and functions to maintain theentire delay through all of delay elements 104-107 to be a single clockcycle. Accordingly, each delay element (e.g. 105) delays the signal by1/n of the clock cycle. Selector 102 may be configured viamicroprocessor 103 to select one of its inputs for conveying to itsoutput 112.

Once the signal V_(f) enters programmable delay 101, a delayed versionof that signal is output onto each of the outputs a₀-a_(n). One of thoseoutputs a₀-a_(n-1) is fed back through selector 112, causing an invertedversion of the signal to be fed into programmable delay 101, andrepeating the cycle all over. Thus, the signal V_(f) will oscillate andcan be tuned at resolutions higher than that of the clock frequency.

The time resolution of the circuit is thus not limited to the frequencyof clock 110. Because the delay of all of elements 104-107 is a singleclock cycle, the resolution achieved by selecting one of the delayedoutputs is n times the resolution that the clock 110 would normallyprovide in prior art circuits. This is shown pictorially in FIG. 3,where t1=the delay programmed into programmable delay 101, m is an indexvariable that ranges in value from 1 to n, and T is the period of V_(f).

FIG. 4 shows an alternative embodiment of the present invention forgenerating a pulse width modulated (PWM) signal. The system includes aprogrammable pulse width modulator circuit 401, a plurality of delayelements 402-405, a delay locked loop 4-6 similar to that of FIG. 2, aselector 408 for selecting one of inputs a₀ through a_(n) to theselector to convey to the selector output, and a logic gate 409connected to the selector output. In operation, the programmable PWMoutputs a PWM signal of a fixed duty cycle set in accordance withinstructions from microprocessor 14. The waveform that is output byprogrammable PWM generator 401 is shown as a₀ in FIG. 5. In accordancewith the inventions, the delay locked loop 406 maintains the delay ofone full clock cycle through delay elements 402-405. Accordingly, eachoutput is delayed by 1/n of the clock frequency, T_(clk).

The selector 408 selects one of the inputs for conveyance to logic gate409, which is shown as an OR gate. The output 411 will be on as long aseither the PWN signal is on, or a delayed version of that signal remainson. Since the delayed version may be delayed by an amount that is lessthan the period of the clock, the PWM signal can have a time resolutionn times not of the clock frequency.

Several exemplary relevant waveforms generated by the arrangement ofFIG. 4 are shown in FIG. 5. a₀ represents the PWM signal produceddirectly at the output of programmable PWM 401. The second signal Crepresents a slightly delayed version of the signal that is conveyedthrough selector 408 as shown in FIG. 4. The resulting PWM signalremains on for an amount of time that may be varied in increments ofT_(clock)/n. The specific delay experienced depends upon which delay isselected by selector 408 in response to instructions from microprocessor410. Delay locked loop 406 maintains the appropriate delays in each ofdelay elements 402-405 such that the delay can be controlled independentof temperature and process variations.

While the foregoing describes the preferred embodiment of theinventions, various other modifications or additions will be apparent tothose who are skilled in the art. Such modification are intended to becovered by the claims appended hereto.

1. Apparatus for increasing the time resolution of a clock in anelectronic device; said apparatus comprising a first delay elementhaving an input for receiving and delaying an input signal by a firstamount of time to produce an output signal; a second delay element fordelaying said output signal by a predetermined fraction of a period ofsaid clock to produce a second output signal; a feedback path fortransmitting said second output signal to said input of said first delayelement and an inverter for inverting either said output signal or saidsecond output signal.
 2. The apparatus of claim 1 wherein the firstdelay element comprises a programmable delay element.
 3. Apparatus ofclaim 2 wherein said second delay element includes plural third delayelements in combination with a selector for selecting one of the pluraldelay elements.
 4. Apparatus of claim 3 further comprising amicroprocessor connected to both the selector and the programmable delayelement for programming the proper delay into the programmable delayelement and for selecting an output from one of said third delayelements to feed back to the input of said programmable delay. 5.Apparatus of claim 4 further comprising a delay lock loop connected tosaid third delay elements to cause total delay introduced by all of saidthird delay elements to be equal to a period of said clock.
 6. Apparatusfor generating a pulse width modulated (PWM) signal from a clock havinglower resolution than that of said PWM signal, said apparatus comprisinga first delay element for delaying an input signal by a firstpredetermined amount to produce a first output signal, a second delayelement for delaying said first output signal by a second predeterminedamount to produce a second output signal, and a logic gate forperforming a logic function with respect to said first and secondoutputs.
 7. Apparatus of claim 6 wherein said logic gate is an OR gateor and AND gate.
 8. Apparatus of claim 7 wherein said second delayelement comprises plural third delay elements and a selector forselecting an output of one of said third delay elements.
 9. Apparatus ofclaim 8 wherein said third delay elements are arranged in series suchthat a total delay introduce by all of said third delay elements isequal to one period of a clock, the clock also being configured to drivethe first delay element.
 10. Apparatus of claim 9 further comprising adelay lock loop for maintaining appropriate delays of each of said thirddelay elements.
 11. A method of producing a Pulse Width Modulated (PWM)signal, said method comprising receiving in an OR gate a first signaland a second signal, the second signal being selected from plural thirdsignals, each of said plural third signals being equal to a delayedversion of said first signal, said delay being equal to T/n, where n isa selected one of a different integer for each of said third signals,and T is a clock signal.
 12. The method of claim 11 further comprisingconnecting a delay lock loop to plural delay elements to generate saidthird signals.
 13. The method of claim 11 wherein an original signal isdelayed by a preprogrammed amount and subsequently by plural delays ofequal value.